Electronics for High-energy Physics Experiments in the Giga-scale Integration Era

VLSI technology is being driven to giga-scale levels of integration with IC minimum feature dimensions approaching atomic scales. System-level integration is now pursued as critical in major commercial applications including wireless communication, computing, and multimedia. On-chip signal integrity, noise, and electromagnetic compliance (EMC) are becoming “showstoppers” in addition to escalating wafer costs. This paper will identify major technology developments and applications in the commercial market and discuss how the high-energy physics community can leverage these advances in years to come. The role of the university research will be discussed as well as new opportunities for collaborative efforts. 1. OVERVIEW AND INTRODUCTION Functional integration is becoming the dominant industry driver, as systems realize the benefits of reduced IC count, shorter interconnect lengths, and lower power dissipation. System integration, which began with digital functions such as processors and memories, is now being extended to include analog signal processing (ADCs and DACs), RF telecommunications, power generation and conditioning, and pixel sensors. Table 1 lists some of the requirements of these integrated systems from the perspective of HEP experiments. Table 1: Performance Requirements System Performance Computing bandwidth > 4 GB/sec Embedded memory > 16 MB Signal processing sensitivity << 1 μV Communications > 40 MB/sec Low bit error rate < 10 -9 Power conditioning < 1% ripple Power levels > 5 kV Radiation hardness > 10 Mrad Temperature ruggedness > 150 °C 1.1 Bulk and SOI CMOS Two flavors of CMOS, bulk and SOI, are available for systems integration, each having specific advantages and limitations. Figure 1 compares the cross sections of a device implemented in bulk and SOI. Figure 1: Comparison of bulk and SOI devices. Bulk has typically better radiation-hardness considering it has no buried oxide with its associated interface traps. SOI, however, offers better isolation given that the buried oxide prevents device crosstalk. Within SOI, both partially and fully depleted implementations are possible. Although fully-depleted SOI provides better electrical performance, the top-gate threshold voltage is linked to the buried oxide potential and is therefore more susceptible to long-term irradiation than PD-SOI. SOI, despite somewhat poorer radiation tolerance, is an ideal candidate for systems integration. The dielectric isolation permits the co-fabrication of many different systems, in which the performance of each can be uniquely optimized. Samples are shown in Fig. 2 of SOI implementations of merged power and logic devices, pixel sensing, and combined mixed-signal and RF functions. Delivering these integrated systems, however, requires the solution to many challenges in signal integrity, noise, EMI, technology optimization, and testability. These issues will be discussed throughout this paper.